• Resumo

    A Low-Power and Performance-Efficient Co-design Implementation of AES Encoder

    Data de publicação: 29/05/2019

    Encryption algorithms are required for a higher safety degree when
    considering, for instance, data exchange in computer networks. AES (Advanced
    Encryption Standard) is an alternative to cipher data and therefore increase
    the security of sensitive data communication. A possible approach for a
    good trade-off of this application regarding processing time, area, power, and
    time-to-market is to use a co-design fashion, where portions of the algorithm
    run in a processor, while other parts operate in hardware accelerators. The
    proposed work, name LP-SB, is a low-power proposal for an AES co-design,
    where the power-critical step of the algorithm (i.e., SubBytes) is ported to an
    accelerator and, therefore, two low-power techniques are inserted for that block.
    Power results running LB-SB on gate-level netlist resulted in around 13% of
    power reduction when compared with the same block without the low-power
    techniques. Moreover, the AES co-design proposed achieves 44-times more
    performance when compared to the software-only solution, which is within the
    expected improvement when compared to related AES co-design works.

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